This application claims the priority of Korean Patent Application No. 2002-55966, filed Sep. 14, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a sense amplifier which is laid out between a sense line and a data line of a memory device having an active restoration function and a semiconductor memory device including a latch-type sense amplifier which utilizes the memory device having the active restoration function as a part of the latch.
2. Description of the Related Art
Semiconductor memory devices may be generally classified as random access memory (RAM) and read only memory (ROM), based on the type of memory cell employed.
A RAM device is capable of the random writing, storing, and reading of data. The RAM is a volatile memory in which data stored therein is lost if supply voltage to the RAM is interrupted.
A dynamic random access memory (DRAM) is a special form of RAM commonly used as a storage device in a computer, in which a memory cell for storing information includes a single storage capacitor and a single transistor for reading data stored in the storage capacitor. Data stored in the memory cell of the DRAM are lost over a certain period of time due to leakage current. Therefore, the DRAM requires a periodic refresh so as to restore data stored in the storage capacitor before the data are lost.
ROM, on the other hand, can preserve data indefinitely, even when the supply voltage to the ROM is blocked. Accordingly, ROM is referred to as a non-volatile memory and thus it does not require a periodic refresh.
The art related to the memory having the active restoration function used in semiconductor memory devices is well described in U.S. Pat. No. 6,169,308.
FIG. 1 is a sectional view of a ROM in the form of a conventional scalable two-transistor memory (STTM), and FIG. 2 is a circuit diagram of the STTM of FIG. 1.
Referring to FIGS. 1 and 2, reference numeral 10 denotes a silicon substrate, 20 denotes a sense line or a bit line, 30 denotes a ground line, 40 denotes a field insulator, 50 denotes an insulator layer such as a gate oxide layer, 60 denotes a data line, 70 denotes a storage node, and 80 denotes a word line or a control gate. Reference numeral 200 denotes a memory cell of the STTM, and Cp denotes a parasitic capacitor.
Data, in the form of charge stored in the storage node 70, are held or read in response to the voltage level supplied on the word line 80. The data or charge provided on the data line 60 is written in the storage node 70 according to the voltage supplied to the word line 80. The voltage level of the word line 80 for writing the data in the data line 60 to the storage node 70 is higher than the voltage level of the word line 80 for reading the data stored in the storage node 70 through the bit line 20.
Reference numeral 210 represents a transistor for reading out the data, and reference numeral 230 is a transistor for writing the data in the data line 60 to the storage node 70.
The STTM of FIGS. 1 and 2 is a non-volatile memory. However, since the characteristics of vertical STTM that are manufactured using a polycrystalline silicon are relatively poor, the information stored in the vertical STTM volatizes, and the read operation of the vertical STTM is therefore a destructive read in which the information stored in the STTM is lost. Therefore, whenever the information stored in the STTM is accessed or read, the STTM requires an active restoration function in which the result of accessing or reading the information is written back to the STTM. The STTM is therefore an example of a memory device having such an active restoration function.
The data in the sense line or the bit line 20 have an opposite polarity, e.g., low, with respect to the polarity, e.g., high, of the data stored in the storage node 70, and thus the corresponding sense amplifier (not shown) amplifies the data in the sense line or the bit line 20 and then writes data having an opposite polarity to the sense line data back into the STTM 200.
Accordingly, in the conventional STTM, an additional circuit for memorizing the number of accesses to the STTM, e.g., an even number or an odd number, and an additional circuit for determining whether the polarity of the data (e.g. negative or positive) stored in the STTM are required.